Four Cores, One Chip

Dual specialization

The CFPU is not a single core multiplied by thousands. Different workloads demand different processor geometries — which is why the CFPU core family branches in two directions from a single common base: the Nano Core.

The first branch grows toward general-purpose programming: Nano → Actor → Rich. Each step adds more SRAM and a richer ISA — Actor is optimized for object handling and GC, Rich for floating-point computation.

The second branch diverges toward security: Nano → Seal. The Seal Core contains cryptographic primitives (SHA-256, WOTS+, Merkle), code authentication, and eFuse management — not a compute core, but a security gatekeeper.

           Nano Core (CIL-T0, base)
              /              \
     Actor (+GC+Obj)     Seal (+Crypto)
        |
     Rich (+FPU)

This dual specialization is unique to the CFPU: no other processor family offers both directions — programming and security — on the same interconnect, with the same message format, parameterized from the same RTL.

ML/SNN inference is handled not by programmable cores but by MAC Slices — FSM-driven compute units even simpler than Nano. These are specified in the CFPU-ML-Max document.

The four core types

Nano Core — spike / sensor

The smallest and most numerous core. Integer arithmetic only, 4–64 KB SRAM, minimal ISA (48 CIL-T0 opcodes), mailbox-based messaging. Designed for sensors, edge processing, and SNN spike propagation — where precision is less important than speed and energy efficiency.

Actor Core — general actor

The CFPU's primary workhorse. Full CIL ISA with object support, GC, generics, and exception handling, 64–256 KB SRAM, mailbox-based messaging. Symphact actors, server logic, general-purpose parallel processing. In most CFPU configurations, this is the dominant core type. In the CFPU-ML chip, Actor Cores handle non-MAC operations (LayerNorm, Softmax, Residual).

Rich Core — FP actor

An extension of the Actor Core with an IEEE-754 floating-point unit (power-gated). 128–512 KB SRAM. Numerical computation, scientific workloads, financial models, complex business logic. The baseline for all external CPU comparisons.

Seal Core — authentication

A security core placed at the chip center (integrated with the L3 crossbar in monolithic CFPU chips, on the IOD in chiplet CFPU-ML). Code authentication (SHA-256, WOTS+, Merkle), key management, eFuse, TRNG, isolation boundary enforcement. Not a compute core — a security gatekeeper. Scales without saturation to ~30,000 cores.

Core comparison table

Property	Nano	Actor	Rich	Seal
ISA	CIL-T0 (48 opcodes, int32)	Full CIL (obj, GC, generics)	Full CIL + FPU	CIL-Seal (CIL-T0 subset + crypto)
FPU	—	—	✓ (IEEE-754, power-gated)	—
GC + Obj	—	✓ (bump alloc, mark-sweep)	✓	—
Exception handling	Trap only	Full (throw/catch/finally)	Full	Trap only
Crypto HW	—	—	—	✓ (SHA-256, WOTS+, Merkle, eFuse, TRNG)
Mailbox	✓	✓	✓	dedicated inbox
SRAM range	4–64 KB	64–256 KB	128–512 KB	~32 KB
Logic (5nm)	0.005 mm²	0.010 mm²	0.012 mm²	~0.11 mm²
Power gating	Per-core clock gating	Per-core clock gating	FPU separate domain	Wake-on-demand

Core count comparison (5nm, chiplet, 18-tine package)

Using the same chiplet layout as CFPU-ML-Max: 85 mm² tine die (5nm), ~83 mm² usable per tine, 18 tines per package (SoIC + CoWoS). Logic includes +25% design margin, SRAM uses ISSCC reference density (0.021 mm²/Mbit).

Core type	SRAM	Core size (5nm)	Cores / tine	Cores / package (18 tine)	Primary use
Nano	4 KB	~0.007 mm²	~10,400	~187,000	Spike / sensor / edge
Actor	64 KB	~0.023 mm²	~3,170	~57,000	General actor / Symphact
Rich	256 KB	~0.057 mm²	~1,280	~23,000	FP compute / scientific code
MAC Slice	8 KB (M SKU)	~0.015 mm²	~5,264	~94,752	ML / SNN inference

The Seal Core resides on the IOD (or at the center of a monolithic chip), in 1+ instances — therefore not included in the table. Core sizes include logic (+25% margin) and SRAM; per-tine counts assume ~12% routing/infrastructure overhead. The MAC Slice row is from the CFPU-ML-Max specification.

CFPU product family

Variant	Primary units	Target platform	Notes
CFPU-N	Seal + Nano	IoT / edge sensor	Maximum core count, minimum power
CFPU-A	Seal + Actor	Server / cloud	Symphact reference platform
CFPU-R	Seal + Rich	Scientific / HPC	FPU + GC, competes with discrete CPUs
CFPU-ML	Seal + MAC Slice + Actor	ML/SNN inference	Chiplet: tine dies + IOD
CFPU-H	Seal + Actor + Nano	Hybrid server	Heterogeneous supervisor + worker
CFPU-X	Mixed (any combination)	Research / prototype	Application-specific

CFPU-ML: the ML/SNN inference chip

The CFPU-ML variant is optimized for ML/SNN inference. It consists not of programmable cores but of MAC Slices (FSM-driven compute units) + Actor Cores + Seal Core. A MAC Slice is not a CIL processor — it has no program counter, it only streams multiply-accumulate operations. Control is handled by Actor Cores.

Detailed chiplet specification, MAC Slice architecture, SKU family, competitive comparison, and model coverage: CFPU-ML-Max: ML/SNN Inference Accelerator →

The CFPU is not a single core — it is four specialized core types + MAC Slice compute units operating on the same chip (or chiplet package), over the same message network. Specialization does not fragment the system: it unifies it.